From e4326b612098fd39e59b43996f92db95b25d6c2c Mon Sep 17 00:00:00 2001
From: Isabelle L <me@izzabelle.dev>
Date: Wed, 24 Jun 2020 13:41:30 -0500
Subject: [PATCH] cleaning up asm a bit

---
 README.md            | 14 ++++++++++++-
 ceres-asm/src/lib.rs | 49 ++++++++++++--------------------------------
 2 files changed, 26 insertions(+), 37 deletions(-)

diff --git a/README.md b/README.md
index cff59a2..18d2bcb 100644
--- a/README.md
+++ b/README.md
@@ -33,7 +33,13 @@ god oh fuck what am i even doing
 
 | opcode  | signifier | destination | padding | immediate/address  |
 | ------- | --------- | ----------- | ------- | ------------------ |
-| `00001` | `100`     | `0000`      | `0000`  | `0000000000000000` |
+| `00001` | `000`     | `0000`      | `0000`  | `0000000000000000` |
+
+##### store - `st:signifier address $source`
+
+| opcode  | signifier | source | padding | address            |
+| ------- | --------- | ------ | ------- | ------------------ |
+| `00100` | `000`     | `0000` | `0000`  | `0000000000000000` |
 
 ##### add - `add $src1 $src2 $dest`
 
@@ -41,3 +47,9 @@ god oh fuck what am i even doing
 | ------- | ----------------- | ------- | ------- | ------ |
 | `00010` | `000000000000000` | `0000`  | `0000`  | `0000` |
 
+##### sub - `sub $source1 $source2 $dest`
+
+| opcode  | padding           | source1 | source2 | dest   |
+| ------- | ----------------- | ------- | ------- | ------ |
+| `00011` | `000000000000000` | `0000`  | `0000`  | `0000` |
+
diff --git a/ceres-asm/src/lib.rs b/ceres-asm/src/lib.rs
index e80a028..f5c5a5e 100644
--- a/ceres-asm/src/lib.rs
+++ b/ceres-asm/src/lib.rs
@@ -45,9 +45,9 @@ impl<'a> Assembler<'a> {
                 Token::Comment => continue,
                 Token::Newline => continue,
                 // cases that like, actually make sense to process
-                Token::Load => machine_code.push(self.load()?),
-                Token::Add => machine_code.push(self.add()?),
-                Token::Sub => machine_code.push(self.sub()?),
+                Token::Load => machine_code.push(self.immediate_instruction(0b00001u32)?),
+                Token::Add => machine_code.push(self.register_instruction(0b00010u32)?),
+                Token::Sub => machine_code.push(self.register_instruction(0b00011u32)?),
                 // cases that should straight up not happen
                 _ => return Err(CeresAsmError::LazyBadToken { token }),
             }
@@ -55,7 +55,7 @@ impl<'a> Assembler<'a> {
         Ok(MachineCode(machine_code))
     }
 
-    // wrapping for lexer.next() with changing to result
+    // wrapping for lexer.next() with option to result
     fn next(&mut self) -> Result<Token> {
         if let Some(token) = self.lexer.next() {
             Ok(token)
@@ -64,47 +64,24 @@ impl<'a> Assembler<'a> {
         }
     }
 
-    // load instruction assembly
-    fn load(&mut self) -> Result<u32> {
-        let opcode = 0b00001u32;
-
-        let token = self.next()?;
-        let signifier = Signifier::from_token(&token)?.as_bits() as u32;
-
+    fn register_instruction(&mut self, opcode: u32) -> Result<u32> {
         let token = self.next()?;
-        let register = token.register_index()? as u32;
-
+        let src_one = token.register_index()? as u32;
         let token = self.next()?;
-        let literal = token.literal()? as u32;
-        Ok((opcode << 27) | (signifier << 24) | (register << 20) | literal)
-    }
-
-    // add instruction assembly
-    fn add(&mut self) -> Result<u32> {
-        let opcode = 0b00010u32;
-
-        let token = self.next()?;
-        let source_one = token.register_index()? as u32;
-        let token = self.next()?;
-        let source_two = token.register_index()? as u32;
+        let src_two = token.register_index()? as u32;
         let token = self.next()?;
         let dest = token.register_index()? as u32;
-
-        Ok((opcode << 27) | (source_one << 8) | (source_two << 4) | dest)
+        Ok((opcode << 27) | (src_one << 8) | (src_two << 4) | (dest))
     }
 
-    // sub instruction assembly
-    fn sub(&mut self) -> Result<u32> {
-        let opcode = 0b00011u32;
-
+    fn immediate_instruction(&mut self, opcode: u32) -> Result<u32> {
         let token = self.next()?;
-        let source_one = token.register_index()? as u32;
+        let signifier = Signifier::from_token(&token)?.as_bits() as u32;
         let token = self.next()?;
-        let source_two = token.register_index()? as u32;
+        let register = token.register_index()? as u32;
         let token = self.next()?;
-        let dest = token.register_index()? as u32;
-
-        Ok((opcode << 27) | (source_one << 8) | (source_two << 4) | dest)
+        let literal = token.literal()? as u32;
+        Ok((opcode << 27) | (signifier << 24) | (register << 20) | literal)
     }
 }