changes to registers and addition of memory module

Cargo.lock

@@ -1,16 +1,98 @@
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+"checksum xkb 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "aec02bc5de902aa579f3d2f2c522edaf40fa42963cbaffe645b058ddcc68fdb2"
+"checksum xkbcommon-sys 0.7.4 (registry+https://github.com/rust-lang/crates.io-index)" = "fa434980dca02ebf28795d71e570dbb78316d095a228707efd6117bf8246d78b"
+"checksum xml-rs 0.8.3 (registry+https://github.com/rust-lang/crates.io-index)" = "b07db065a5cf61a7e4ba64f29e67db906fb1787316516c4e6e5ff0fea1efcd8a"

Cargo.toml

@@ -5,5 +5,5 @@ authors = ["Izzy <me@izzabelle.dev>"]
 edition = "2018"
 
 [dependencies]
-byteorder = "1.3.2"
 logos = "0.9.7"
+offbrand = { git = "https://github.com/izzabelle/offbrand" }

README.md

@@ -1,2 +1,22 @@
 # Ceres 
-### a shitty fantasy console written in rust usng a proprietary asm instruction set
+a shitty fantasy console written in rust using a proprietary MIPS based asm instruction set. a bit of inspiration from PICO-8
+
+### GRAPHICS
+
+uhhhhh funny 128x72 screen
+
+### Register layout and info
+
+all registers are unsigned 16 bit
+
+| Register number | Register name | Register usage       |
+| --------------- | ------------- | -------------------- |
+| 0               | z0            | always contains zero |
+| 1               | gp            | global pointer       |
+| 2               | gp            | stack pointer        |
+| 3               | ra            | return address       |
+| 4-6             | a0-a2         | argument registers   |
+| 7               | v0            | return register      |
+| 8               | v1            | return register 2    |
+| 9-15            | t0-t6         | temporary registers  |
+

src/cpu.rs

@@ -1,106 +0,0 @@
-/// 16 register cpu only capable of holding 16 bit unsigned integers
-pub struct Cpu {
-    // zero register
-    z0: u16,
-
-    // system registers
-    sp: u16,
-    ra: u16,
-
-    // argument registers
-    a0: u16,
-    a1: u16,
-    a2: u16,
-
-    // return registers
-    v0: u16,
-    v1: u16,
-
-    // temp registers
-    t0: u16,
-    t1: u16,
-    t2: u16,
-    t3: u16,
-    t4: u16,
-    t5: u16,
-    t6: u16,
-    t7: u16,
-}
-
-/// initializes cpu with 0x00 in all registers
-impl Default for Cpu {
-    fn default() -> Self {
-        Cpu {
-            z0: 0,
-            sp: 0,
-            ra: 0,
-            a0: 0,
-            a1: 0,
-            a2: 0,
-            v0: 0,
-            v1: 0,
-            t0: 0,
-            t1: 0,
-            t2: 0,
-            t3: 0,
-            t4: 0,
-            t5: 0,
-            t6: 0,
-            t7: 0,
-        }
-    }
-}
-
-/// indexes registers by register number and returns reference to the registers
-/// contents
-impl std::ops::Index<usize> for Cpu {
-    type Output = u16;
-
-    fn index(&self, idx: usize) -> &u16 {
-        match idx {
-            0 => &self.z0,
-            1 => &self.sp,
-            2 => &self.ra,
-            3 => &self.a0,
-            4 => &self.a1,
-            5 => &self.a2,
-            6 => &self.v0,
-            7 => &self.v1,
-            8 => &self.t0,
-            9 => &self.t1,
-            10 => &self.t2,
-            11 => &self.t3,
-            12 => &self.t4,
-            13 => &self.t5,
-            14 => &self.t6,
-            15 => &self.t7,
-            _ => panic!("Invalid register number"),
-        }
-    }
-}
-
-/// indexes registers by register number and returns mutable reference to the
-/// registers contents
-impl std::ops::IndexMut<usize> for Cpu {
-    fn index_mut(&mut self, idx: usize) -> &mut u16 {
-        match idx {
-            0 => &mut self.z0,
-            1 => &mut self.sp,
-            2 => &mut self.ra,
-            3 => &mut self.a0,
-            4 => &mut self.a1,
-            5 => &mut self.a2,
-            6 => &mut self.v0,
-            7 => &mut self.v1,
-            8 => &mut self.t0,
-            9 => &mut self.t1,
-            10 => &mut self.t2,
-            11 => &mut self.t3,
-            12 => &mut self.t4,
-            13 => &mut self.t5,
-            14 => &mut self.t6,
-            15 => &mut self.t7,
-            _ => panic!("Invalid register number"),
-        }
-    }
-}

src/lib.rs

@@ -1,7 +1,16 @@
-pub mod cpu;
+mod memory;
+mod registers;
 
-use cpu::Cpu;
+pub use memory::Memory;
+pub use registers::Registers;
 
 pub struct System {
-    cpu: Cpu,
+    pub registers: Registers,
+    pub memory: Memory,
+}
+
+impl System {
+    pub fn init() -> System {
+        System { registers: Registers::init(), memory: Memory::init() }
+    }
 }

src/main.rs

@@ -1,3 +1,4 @@
 fn main() {
-    println!("Hello, world!");
+    let sys = ceres::System::init();
+    println!("{}", sys.registers);
 }

src/memory.rs

@@ -0,0 +1,10 @@
+/// all the memory as one big fat fucking slice
+pub struct Memory {
+    pub data: [u16; std::u16::MAX as usize],
+}
+
+impl Memory {
+    pub fn init() -> Memory {
+        Memory { data: [0x00; std::u16::MAX as usize] }
+    }
+}

src/registers.rs

@@ -0,0 +1,119 @@
+use std::fmt;
+
+/// 16 register cpu only capable of holding 16 bit unsigned integers
+pub struct Registers {
+    // zero register
+    z0: u16,
+
+    // system registers
+    gp: u16,
+    sp: u16,
+    ra: u16,
+
+    // argument registers
+    a0: u16,
+    a1: u16,
+    a2: u16,
+
+    // return registers
+    v0: u16,
+    v1: u16,
+
+    // temp registers
+    t0: u16,
+    t1: u16,
+    t2: u16,
+    t3: u16,
+    t4: u16,
+    t5: u16,
+    t6: u16,
+}
+
+impl Registers {
+    /// initializes cpu with 0x00 in all registers
+    pub fn init() -> Registers {
+        Registers {
+            z0: 0x00,
+            gp: 0x00,
+            sp: 0x00,
+            ra: 0x00,
+            a0: 0x00,
+            a1: 0x00,
+            a2: 0x00,
+            v0: 0x00,
+            v1: 0x00,
+            t0: 0x00,
+            t1: 0x00,
+            t2: 0x00,
+            t3: 0x00,
+            t4: 0x00,
+            t5: 0x00,
+            t6: 0x00,
+        }
+    }
+}
+
+/// indexes registers by register number and returns reference to the registers
+/// contents
+impl std::ops::Index<usize> for Registers {
+    type Output = u16;
+
+    fn index(&self, idx: usize) -> &u16 {
+        match idx {
+            0 => &self.z0,
+            1 => &self.gp,
+            2 => &self.sp,
+            3 => &self.ra,
+            4 => &self.a0,
+            5 => &self.a1,
+            6 => &self.a2,
+            7 => &self.v0,
+            8 => &self.v1,
+            9 => &self.t0,
+            10 => &self.t1,
+            11 => &self.t2,
+            12 => &self.t3,
+            13 => &self.t4,
+            14 => &self.t5,
+            15 => &self.t6,
+            _ => panic!("Invalid register number"),
+        }
+    }
+}
+
+/// indexes registers by register number and returns mutable reference to the
+/// registers contents
+impl std::ops::IndexMut<usize> for Registers {
+    fn index_mut(&mut self, idx: usize) -> &mut u16 {
+        match idx {
+            0 => &mut self.z0,
+            1 => &mut self.gp,
+            2 => &mut self.sp,
+            3 => &mut self.ra,
+            4 => &mut self.a0,
+            5 => &mut self.a1,
+            6 => &mut self.a2,
+            7 => &mut self.v0,
+            8 => &mut self.v1,
+            9 => &mut self.t0,
+            10 => &mut self.t1,
+            11 => &mut self.t2,
+            12 => &mut self.t3,
+            13 => &mut self.t4,
+            14 => &mut self.t5,
+            15 => &mut self.t6,
+            _ => panic!("Invalid register number"),
+        }
+    }
+}
+
+impl fmt::Display for Registers {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "-- registers ----------------------------------------------------------------------------\n\
+| z0: 0x{:02X} | gp: 0x{:02X} | sp: 0x{:02X} | ra: 0x{:02X} | a0: 0x{:02X} | a1: 0x{:02X} | a2: 0x{:02X} | v0: 0x{:02X} |\n\
+| v1: 0x{:02X} | t0: 0x{:02X} | t1: 0x{:02X} | t2: 0x{:02X} | t3: 0x{:02X} | t4: 0x{:02X} | t5: 0x{:02X} | t6: 0x{:02X} |\n\
+-----------------------------------------------------------------------------------------",
+                 self[0], self[1], self[2], self[3], self[4], self[5], self[6], self[7],
+                 self[8], self[9], self[10], self[11], self[12], self[13], self[14], self[15])
+    }
+}